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general description the MAX5098A is a dual-output, high-switching-frequen- cy dc-dc converter with integrated n-channel switches that can be used either in high-side or low-side configura- tion. each output can be configured either as a buck con- verter or a boost converter. in the buck configuration, this device delivers up to 2a from converter 1 and 1a from converter 2. the MAX5098A also integrates a load-dump protection circuitry that is capable of handling load-dump transients up to 80v for automotive applications. the load-dump protection circuit utilizes an internal charge- pump to drive the gate of an external n-channel mosfet. when an overvoltage or load-dump condition occurs, the series protection mosfet absorbs the high voltage tran- sient to prevent damage to lower voltage components. the dc-dc converters operate over a wide operating voltage range from 4.5v to 19v. the MAX5098A oper- ates 180 out-of-phase with an adjustable switching fre- quency to minimize external components while allowing the ability to make trade-offs between the size, efficiency, and cost. the high switching frequency (up to 2.2mhz) also allows this device to operate outside the am band for automotive applications. this device utilizes voltage-mode control for stable oper- ation and external compensation, thus the loop gain is tailored to optimize component selection and transient response. this device can be synchronized to an exter- nal clock fed at the sync input. also, a clock output (cko) allows a master-slave connection of two devices with a four-phase synchronized switching sequence. additional features include internal digital soft-start, indi- vidual enable for each dc-dc regulator (en1 and en2), open-drain power-good outputs (pgood1 and pgood2), and a shutdown input (on/off). other features of the MAX5098A include overvoltage pro- tection, short-circuit (hiccup current limit) and thermal protection. the MAX5098A is available in a thermally enhanced, exposed pad, 5mm x 5mm, 32-pin tqfn package and is fully specified over the automotive -40? to +125? temperature range. applications automotive am/fm radio power supply automotive instrument cluster display features wide 4.5v to 5.5v or 5.2v to 19v input voltage range (with up to 80v load-dump protection) dual-output dc-dc converter with integrated power mosfets each output configurable in buck or boost mode adjustable outputs from 0.8v to 0.85v in buck configuration) and from v in to 28v (boost configuration) i out1 and i out2 of 2a and 1a (respectively) in buck configuration switching frequency programmable from 200khz to 2.2mhz synchronization input (sync) clock output (cko) for four-phase master-slave operation individual converter enable input and power- good output low-i q (7?) standby current (on/off) internal digital soft-start and soft-stop short-circuit protection on outputs and maximum duty-cycle limit overvoltage protection on outputs with auto restart thermal shutdown thermally enhanced 32-pin tqfn package dissipates up to 2.7w at +70? MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ________________________________________________________________ maxim integrated products 1 ordering information 19-4111; rev 0; 5/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet evaluation kit available + denotes a lead-free package. * ep = exposed pad. part temp range pin-package MAX5098Aatj+ -40? to +125? 32 tqfn-ep*
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (vdrv = v l , v+ = v l = in_high = 5.2v or v+ = in_high = 5.2v to 19v, en_ = v l , sync = gnd, i vl = 0ma, pgnd_ = sgnd, c bypass = 0.22? (low esr), c vl = 4.7? (ceramic), c v+ = 1? (low esr), c in_high = 1? (ceramic), r in_high = 3.9k , r osc = 10k , t j = -40? to +125?, unless otherwise noted.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specifications. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . v+ to sgnd............................................................-0.3v to +25v v+ to in_high...........................................................-19v to +6v in_high to sgnd ..................................................-0.3v to +19v in_high maximum input current .......................................60ma bypass to sgnd..................................................-0.3v to +2.5v gate to v+.............................................................-0.3v to +12v gate to sgnd .......................................................-0.3v to +36v sgnd to pgnd_ ...................................................-0.3v to +0.3v v l to sgnd ..................-0.3v to the lower of +6v or (v+ + 0.3v) vdrv to sgnd .........................................................-0.3v to +6v bst1/vdd1, bst2/vdd2, drain_, pgood_ to sgnd ..............................................-0.3v to +30v on/off to sgnd ...............................-0.3v to (in_high + 0.3v) bst1/vdd1 to source1, bst2/vdd2 to source2......................................-0.3v to +6v source_ to sgnd................................................-0.6v to +25v source_ to pgnd_.................................................-1v for 50ns en_ to sgnd............................................................-0.3v to +6v osc, fsel_1, comp_, sync, fb_ to sgnd..............................................-0.3v to (v l + 0.3v) cko to sgnd..........................................-0.3v to (vdrv + 0.3v) source1, drain1 peak current ..............................5a for 1ms source2, drain2 peak current ..............................3a for 1ms v l , bypass to sgnd short circuit ................... continuous, internally limited continuous power dissipation (t a = +70?) 32-pin tqfn-ep (derate 34.5mw/? above +70?)..2759mw package junction-to-ambient thermal resistance ( ja ) (note 1).............................29.0?/w package junction-to-case thermal resistance ( jc ) (note 1) ..............................1.7?/w operating temperature range .........................-40? to +125? storage temperature range ............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units system specifications v+ = in_high 5.2 19 input voltage range v+ v l = v+ = in_high (note 3) 4.5 5.5 v v+ operating supply current i q v l unloaded, no switching 4.2 ma v+ standby supply current i v+stby v en_ = 0v, pgood_ unconnected, v+ = v in_high = 14v 0.75 1.1 ma v+ = v l = 5.2v 78 v+ = 12v 76 efficiency (v out1 = 5v at 1.5a, v out2 = 3.3v at 0.75a, f sw = 1.85mhz v+ = 16v 70 % overvoltage protector in_high clamp voltage in_high i sink = 10ma 19 20 21 v in_high clamp load regulation 1ma < i sink < 50ma 160 mv in_high supply current i in_high v en_ = v pgood_ = v gate = 0v, v in_high = v on/off = 14v 270 600 ? in_high standby supply current i in_highstby v on/off = 0v , p good _ = v + = unconnected, v in_high = 14v , t a = -40? to +85? 79a v+ to in_high overvoltage clamp v ov v ov = v+ - v in_high , i gate = 0ma (sinking) 1.2 1.85 2.5 v
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units rising, on/off = in_high, gate rising 3.6 4.1 in_high startup voltage in_high uvlo falling, on/off = in_high, gate falling 3.45 v gate charge current i gate_ch v in_high = v on/off = 14v, v gate = v+ = 0v 20 45 80 ? v+ = v in_high = v on/off = 4.5v, i gate = 1?, sourcing 4.0 5.3 7.5 gate output voltage v gate - v in_high v+ = v in_high = v on/off = 14v, i gate = 1?, sourcing 9 v gate turn-off pulldown current i gate_pd v in_high = 14v, v on/off = 0v, v+ = 0v, v gate = 5v, sinking 3.6 ma startup/v l regulator v l undervoltage lockout trip level uvlo v l falling 3.9 4.1 4.3 v v l undervoltage lockout hysteresis 180 mv v l output voltage v l i source_ = 0 to 40ma, 5.5v v+ 19v 5.0 5.2 5.5 v v l ldo short-circuit current i vl_short v+ = v in_high = 5.2v 130 ma v l ldo dropout voltage v ldo i source_ = 40ma, v+ = v in_high = 4.5v 300 550 mv bypass output bypass voltage v bypass i bypass = 0? 1.98 2.00 2.02 v bypass load regulation v bypass 0 < i bypass < 100? (sourcing) 2 5 mv soft-start/soft-stop digital ramp period soft- start/soft-stop internal 6-bit dac 2048 f sw clock cycles soft-start/soft-stop 64 steps voltage-error amplifier fb_ input bias current i fb_ 250 na -40? t a +85? 0.783 0.8 0.809 fb_ input voltage set point v fb_ -40? t a +125? 0.785 0.814 v fb_ to comp_ transconductance g m 1.4 2.4 3.4 ms internal mosfets i switch = 100ma, bst1/vdd1 to v source1 = 5.2v 195 on-resistance high-side mosfet converter 1 r on1 i switch = 100ma, bst1/vdd1 to v source1 = 4.5v 208 355 m electrical characteristics (continued) (vdrv = v l , v+ = v l = in_high = 5.2v or v+ = in_high = 5.2v to 19v, en_ = v l , sync = gnd, i vl = 0ma, pgnd_ = sgnd, c bypass = 0.22? (low esr), c vl = 4.7? (ceramic), c v+ = 1? (low esr), c in_high = 1? (ceramic), r in_high = 3.9k , r osc = 10k , t j = -40? to +125?, unless otherwise noted.) (note 2)
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 4 _______________________________________________________________________________________ electrical characteristics (continued) (vdrv = v l , v+ = v l = in_high = 5.2v or v+ = in_high = 5.2v to 19v, en_ = v l , sync = gnd, i vl = 0ma, pgnd_ = sgnd, c bypass = 0.22? (low esr), c vl = 4.7? (ceramic), c v+ = 1? (low esr), c in_high = 1? (ceramic), r in_high = 3.9k , r osc = 10k , t j = -40? to +125?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units i switch = 100ma, bst2/vdd2 to v source2 = 5.2v 280 on-resistance high-side mosfet converter 2 r on2 i switch = 100ma, bst2/vdd2 to v source2 = 4.5v 300 520 m minimum converter 1 output current i out1 v out1 = 5v, v+ = 12v (note 4) 2 a minimum converter 2 output current i out2 v out2 = 3.3v, v+ = 12v (note 4) 1 a converter 1/converter 2 mosfet drain_ leakage current i lk12 v en1 = v en2 = 0v, v drain_ = 19v, v source_ = 0v 20 ? internal weak low-side switch on-resistance r onlssw_ i lssw = 30ma 22 internal switch current limit internal switch current-limit converter 1 i cl1 v+ = v in_high = 5.2v, v l = vdrv = v bst_/vdd_ = 5.2v 2.8 3.45 4.3 a internal switch current-limit converter 2 i cl2 v+ = v in_high = 5.2v, v l = vdrv = v bst_/vdd_ = 5.2v 1.75 2.1 2.6 a switching frequency pwm maximum duty cycle d max sync = sgnd, f sw = 1.25mhz 82 90 95 % switching frequency range f sw 200 2200 khz switching frequency f sw r osc = 6.81k , each converter (fsel_1 = v l ) 1.7 1.9 2.1 mhz 5.6k < r osc < 10k , 1% 5 switching frequency accuracy 10k < r osc < 62.5k , 1% 7 % sync frequency range f sync sync input frequency is twice the individual converter frequency, fsel_1 = v l (see the setting the switching frequency section) 400 4400 khz sync high threshold v synch 2v sync low threshold v syncl 0.8 v sync input leakage i sync_leak 2a sync input minimum pulse width t syncin 100 ns clock output phase delay cko phase r osc = 62.5k , with respect to converter 2/source2 waveform 40 d eg r ees sync to source 1 phase delay sync phase r osc = 62.5k 90 d eg r ees clock output high level v ckoh v l = 5.2v, sourcing 5ma 3.6 v clock output low level v ckol v l = 5.2v, sinking 5ma 0.6 v
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection _______________________________________________________________________________________ 5 electrical characteristics (continued) (vdrv = v l , v+ = v l = in_high = 5.2v or v+ = in_high = 5.2v to 19v, en_ = v l , sync = gnd, i vl = 0ma, pgnd_ = sgnd, c bypass = 0.22? (low esr), c vl = 4.7? (ceramic), c v+ = 1? (low esr), c in_high = 1? (ceramic), r in_high = 3.9k , r osc = 10k , t j = -40? to +125?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units fsel_1 fsel_1 input high threshold v ih 2v fsel_1 input low threshold v il 0.8 v fsel_1 input leakage i fsel_1_leak 2a on/off on/off input high threshold v ih 2v on/off input low threshold v il 0.8 v on/off input leakage current i on/off_leak v on/off = 5v 0.26 2.00 ? en_ inputs en_ input high threshold v ih en_ rising 1.9 2.0 2.1 v en_ input hysteresis v en_hys 0.5 v en_ input leakage current i en_leak -1 +1 ? power-good output (pgood1, pgood2) pgood_ threshold v tpgood_ falling 90 92.5 95 % v fb_ pgood_ output voltage v pgood_ i sink = 3ma 0.4 v pgood_ output leakage current i lkpgood_ v+ = v l = v in_high = v en_ = 5.2v, v pgood_ = 23v, v fb_ = 1v 2a output overvoltage protection fb_ ovp threshold rising v ovp_r 107 114 121 % v fb_ fb_ ovp threshold falling v ovp_f 12.5 v thermal protection thermal shutdown t shdn rising +165 ? thermal hysteresis t hyst 20 ? note 2: 100% tested at t a = +25? and t a = +125?. specifications at t a = -40? are guaranteed by design and not production tested. note 3: operating supply range (v+) is guaranteed by v l line regulation test. connect v+ to in_high and v l for 5v operation. note 4: output current is limited by the power dissipation of the package; see the power dissipation section in the applications information section.
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 6 _______________________________________________________________________________________ typical operating characteristics (see the typical application circuit , unless otherwise noted. v+ = v in_high = 14v, unless otherwise noted. v+ = v in_high means that n1 is shorted externally.) output1 efficiency vs. load current MAX5098A toc01 load (a) output1 efficiency (%) 1.8 1.6 1.2 1.4 0.6 0.8 1.0 0.4 10 20 30 40 50 60 70 80 90 100 0 0.2 2.0 v in = 8v v in = 14v v in = 16v v out = 5v f sw = 1.85mhz output2 efficiency vs. load current MAX5098A toc02 load (a) output2 efficiency (%) 0.9 0.8 0.6 0.7 0.4 0.5 0.3 0.2 1.0 10 20 30 40 50 60 70 80 90 100 0 v in = 16v v in = 8v v in = 14v v in = 5.5v v in = 4.5v v out = 3.3v f sw = 1.85mhz output1 efficiency vs. load current MAX5098A toc03 load (a) output1 efficiency (%) 1.8 1.6 1.2 1.4 0.6 0.8 1.0 0.4 10 20 30 40 50 60 70 80 90 100 0 0.2 2.0 v in = 8v v in = 14v v in = 16v v out = 5v f sw = 300khz l1 = 18 h output2 efficiency vs. load current MAX5098A toc04 load (a) output2 efficiency (%) 0.9 0.8 0.6 0.7 0.4 0.5 0.3 0.2 1.0 10 20 30 40 50 60 70 80 90 100 0 v in = 16v v in = 8v v in = 14v v in = 5.5v v in = 4.5v v out = 3.3v f sw = 300khz l2 = 27 h output1 voltage vs. load current MAX5098A toc05 load (a) output1 voltage (v) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 4.92 4.94 4.96 4.98 5.00 4.90 0.2 2.0 v in = 8v v in = 14v v in = 16v v out = 5v f sw = 1.85mhz output2 voltage vs. load current MAX5098A toc06 load (a) output2 voltage (v) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 3.22 3.24 3.26 3.28 3.30 3.20 0.2 1.0 v in = 5.5v v in = 16v v in = 14v v out = 3.3v f sw = 1.85mhz v l output voltage vs. converter switching frequency MAX5098A toc07 converter switching frequency (khz) v l output voltage (v) 1700 1200 700 4.2 4.4 4.6 4.8 5.0 5.2 5.4 4.0 200 2200 v in = 4.5v v in = 5.5v v in = 8v v in = 19v v in = 5v both converters switching fsel_1 = v l each converter switching frequency vs. r osc MAX5098A toc08 r osc (k ) switching frequency (mhz) 60 40 20 1 0 80 10 0.1 converter 1, converter 2 converter 1 fsel_1 = v l , fsel_1 = gnd, each converter switching frequency vs. temperature MAX5098A toc09 temperature ( c) switching frequency (mhz) -5 30 65 100 1 10 0.1 -40 135 0.3mhz 0.6mhz 1.25mhz 1.85mhz 2.2mhz fsel_1 = v l
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection _______________________________________________________________________________________ 7 line-transient response (buck converter) MAX5098A toc10 1ms/div v in 5v/div v out1 = 5.0v/1.5a ac-coupled 200mv/div v out2 = 3.3v/0.75a ac-coupled 200mv/div 0v converter 1 load-transient response MAX5098A toc11 100 s/div v out1 = 5.0v ac-coupled 200mv/div i out1 1a/div 0a converter 2 load-transient response MAX5098A toc12 100 s/div v out2 = 3.3v ac-coupled 200mv/div i out2 500ma/div 0a soft-start/soft-stop from en1 MAX5098A toc13 1ms/div v out1 = 5v/2a 5v/div en1 5v/div p good1 5v/div 0v 0v 0v f sw = 1.85mhz soft-start from on/off MAX5098A toc14 2ms/div v out1 = 5v/2a 5v/div on/off 5v/div gate 10v/div v+ 10v/div v l = en1 = en2 5v/div 0v 0v 0v 0v out-of-phase operation (fsel_1 = v l ) MAX5098A toc15 200ns/div source2 10v/div source1 10v/div cko 5v/div 0v 0v 0v typical operating characteristics (continued) (see the typical application circuit , unless otherwise noted. v+ = v in_high = 14v, unless otherwise noted. v+ = v in_high means that n1 is shorted externally.)
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 8 _______________________________________________________________________________________ out-of-phase operation (fsel_1 = sgnd) MAX5098A toc16 200ns/div source2 10v/div source1 10v/div cko 5v/div 0v 0v 0v external synchronization (fsel_1 = v l ) MAX5098A toc17 200ns/div source2 10v/div source1 10v/div cko 5v/div 0v 0v sync 5v/div 0v 0v external synchronization (fsel_1 = sgnd ) MAX5098A toc18 200ns/div source2 10v/div source1 10v/div cko 5v/div 0v 0v sync 5v/div 0v 0v four-phase operation (fsel_1 = v l ) MAX5098A toc19 200ns/div master source1 20v/div master source2 20v/div slave source1 20v/div slave source2 20v/div master cko 5v/div 0v 0v 0v 0v 0v ovp behavior MAX5098A toc20 1ms/div v+ 10v/div gate 10v/div v out1 10v/div pgood2 10v/div v out2 10v/div external overvoltage removed 0v 0v 0v 0v 0v fb_ voltage vs. temperature MAX5098A toc21 temperature ( c) fb_ voltage (v) 100 65 -5 30 0.790 0.795 0.800 0.805 0.815 0.810 0.820 0.825 0.785 -40 135 v l = v+ = v in_high = 5.5v typical operating characteristics (continued) (see the typical application circuit , unless otherwise noted. v+ = v in_high = 14v, unless otherwise noted. v+ = v in_high means that n1 is shorted externally.)
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection _______________________________________________________________________________________ 9 bypass voltage vs. temperature MAX5098A toc22 temperature ( c) bypass voltage (v) 100 65 -5 30 1.994 1.996 1.998 2.000 2.002 2.006 2.004 2.008 2.010 1.990 1.992 -40 135 v l = v+ = v in_high = 5.5v bypass voltage vs. bypass current MAX5098A toc23 bypass current ( a) bypass voltage (v) 80 60 20 40 1.992 1.994 1.998 1.996 2.000 1.990 0 100 70 50 10 30 90 t a = +25 c t a = +135 c t a = +125 c t a = +85 c t a = -40 c source1, source1 indicator current, source2, source2 indicator current MAX5098A toc24 1 s/div i source1 500ma/div no load source1 20v/div no load source2 20v/div i source2 1a/div 0v 0a 0a 0v typical operating characteristics (continued) (see the typical application circuit , unless otherwise noted. v+ = v in_high = 14v, unless otherwise noted. v+ = v in_high means that n1 is shorted externally.) v+ switching supply current vs. switching frequency MAX5098A toc25 switching frequency (khz) v+ switching supply current (ma) 1820 1440 1060 680 10 20 30 40 50 0 300 2200 t a = +25 c t a = +135 c t a = +125 c t a = +85 c t a = -40 c v+ = in_high = on/off v+ standby supply current vs. temperature MAX5098A toc26 temperature ( c) v+ standby supply current (ma) 100 50 0 1 2 3 4 0 -50 150 f sw = 1.85mhz f sw = 300khz v+ = in_high = on/off en1 = en2 = sgnd in_high shutdown current vs. temperature MAX5098A toc27 temperature ( c) in_high shutdown current ( a) 100 50 0 4 8 12 16 20 0 -50 150 in_high = 8v in_high = 14v in_high = 16v on/off = sgnd in_high standby current vs. temperature MAX5098A toc28 temperature ( c) in_high standby current ( a) 100 50 0 85 95 105 115 125 135 145 75 -50 150 in_high = 8v in_high = 14v in_high = 16v on/off = in_high en1 = en2 = sgnd
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 10 ______________________________________________________________________________________ typical operating characteristics (continued) (see the typical application circuit , unless otherwise noted. v+ = v in_high = 14v, unless otherwise noted. v+ = v in_high means that n1 is shorted externally.) in_high clamp voltage vs. clamp current MAX5098A toc29 clamp current (ma) in_high clamp voltage (v) 40 30 20 10 20.0 20.1 20.2 20.3 19.9 050 t a = +25 c t a = +135 c t a = +125 c t a = +85 c t a = -40 c v+ to in_high clamp voltage vs. gate sink current MAX5098A toc30 gate sink current (ma) v+ to in_high clamp voltage (v) 8 6 4 2 1 2 3 4 5 0 010 t a = +25 c t a = +135 c t a = +125 c t a = +85 c t a = -40 c (v gate - v) vs. v in_high MAX5098A toc31 v in_high (v) (v gate - v) (v) 15.5 12.0 8.5 2 4 6 8 10 0 5.0 19.0 t a = +25 c t a = +135 c t a = +125 c t a = +85 c t a = -40 c on/off = in_high system turn-on from battery MAX5098A toc32 10ms/div v l 10v/div v+ 10v/div gate 10v/div in_high 10v/div v in 10v/div 0v 0v 0v 0v 0v system turn-off from battery MAX5098A toc33 10ms/div v l 10v/div v+ 10v/div gate 10v/div in_high 10v/div v in 10v/div 0v 0v 0v 0v 0v system load-dump MAX5098A toc34 100ms/div v out1 ac-coupled 100mv/div v+ 10v/div gate 10v/div in_high 10v/div 0v 0v 0v 0v 0v v in 50v/div
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 11 pin description pin name function 1, 32 source2 converter 2 internal mosfet source connection. for buck converter operation, connect source2 to the switched side of the inductor. for boost operation, connect source2 to pgnd_ (figure 6). 2, 3 drain2 converter 2 internal mosfet drain connection. for buck converter operation, use the mosfet as a high- side switch and connect drain2 to the dc-dc converters supply input rail. for boost converter operation, use the mosfet as a low-side switch and connect drain2 to the inductor and diode junction (figure 6). 4 pgood2 converter 2 open-drain power-good output. pgood2 goes low when converter 2? output falls below 92.5% of its set regulation voltage. use pgood2 and en1 to sequence the converters. converter 2 starts first. 5 en2 converter 2 active-high enable input. connect to v l for always-on operation. 6 fb2 converter 2 feedback input. connect fb2 to a resistive divider between converter 2? output and sgnd to adjust the output voltage. to set the output voltage below 0.8v, connect fb2 to a resistive voltage-divider from bypass to regulator 2? output (figure 3). see the setting the output voltage section. 7 comp2 converter 2 internal transconductance amplifier output. see the compensation section. 8 osc oscillator frequency set input. connect a resistor from osc to sgnd (r osc ) to set the switching frequency (see the setting the switching frequency section). set r osc for an oscillator frequency equal to the sync input frequency when using external synchronization. r osc is still required when an external clock is connected to the sync input. see the synchronization (sync)/clock output (cko) section. 9 sync external clock synchronization input. connect sync to a 400khz to 4400khz clock to synchronize the switching frequency with the system clock. each converter frequency is 1/2 of the frequency applied to sync (fsel_1 = v l ). for fsel_1 = sgnd, the switching frequency of converter 1 becomes 1/4 of the sync frequency. connect sync to sgnd when not used. 10 gate gate drive output. connect to the gate of the external n-channel load-dump protection mosfet. gate = in_high + 9v (typ) with in_high = 12v. gate pulls to in_high by an internal n-channel mosfet when v+ raises 2v above in_high. leave gate unconnected if the load-dump protection is not used (mosfet not installed). 11 on/off n-channel switch enable input. drive on/off high for normal operation. drive on/off low to turn off the external n-channel load-dump protection mosfet and reduce the supply current to 7? (typ). when on/off is driven low, both dc-dc converters are disabled and the pgood_ outputs are driven low. connect to v+ if the external load-dump protection is not used (mosfet not installed). 12 in_high startup input. in_high is protected by internally clamping to 21v (max). connect a resistor (4k max) from in_high to the drain of the protection switch. bypass in_high with a 4.7? electrolytic or 1? minimum ceramic capacitor. connect to v+ if the external load-dump protection is not used (mosfet not installed). 13 v+ input supply voltage. v+ can range from 5.2v to 19v. connect v+, in_high, and v l together for 4.5v to 5.5v input operation. bypass v+ to sgnd with a 1? minimum ceramic capacitor. 14 v l internal regulator output. the v l regulator is used to supply the drive current at input vdrv. when driving vdrv, use an rc lowpass filter to decouple switching noise from vdrv to the v l regulator (see the typical application circuit ). bypass v l to sgnd with a 4.7? minimum ceramic capacitor. 15 sgnd signal ground. connect sgnd to exposed pad and to the board signal ground plane. connect the board signal ground and power ground planes together at a single point.
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 12 ______________________________________________________________________________________ pin description (continued) pin name function 16 bypass reference output bypass connection. bypass to sgnd with a 0.22? or greater ceramic capacitor. 17 fsel_1 converter 1 frequency select input. connect fsel_1 to v l for normal operation. connect fsel_1 to sgnd to reduce converter 1? switching frequency to 1/2 of converter 2? switching frequency (converter 1 switching frequency is 1/4 the cko frequency). do not leave fsel_1 unconnected. 18 comp1 converter 1 internal transconductance amplifier output. see the compensation section. 19 fb1 converter 1 feedback input. connect fb1 to a resistive divider between converter 1? output and sgnd to adjust the output voltage. to set the output voltage below 0.8v, connect fb1 to a resistive voltage-divider from bypass to regulator 1? output (figure 3). see the setting the output voltage section. 20 en1 converter 1 active-high enable input. connect to v l for an always-on operation. 21 pgood1 converter 1 open-drain power-good output. pgood1 output goes low when converter 1? output falls below 92.5% of its set regulation voltage. use pgood1 and en2 to sequence the converters. converter 1 starts first. 22, 23 drain1 converter 1 internal mosfet drain connection. for buck converter operation, use the mosfet as a high- side switch and connect drain1 to the dc-dc converters supply input rail. for boost converter operation, use the mosfet as a low-side switch and connect drain1 to the inductor and diode junction (figure 6). 24, 25 source1 converter 1 internal mosfet source connection. for buck operation, connect source1 to the switched side of the inductor. for boost operation, connect source1 to pgnd_ (figure 6). 26 bst1/vdd1 converter 1 bootstrap flying-capacitor connection. for buck converter operation, connect bst1/vdd1 to a 0.1? ceramic capacitor and diode according to the typical application circuit . for boost converter operation, driver bypass capacitor connection. connect to vdrv and bypass with a 0.1? ceramic capacitor to pgnd_ (figure 6). 27 vdrv low-side driver supply input. connect vdrv to v l through an rc filter to bypass switching noise to the internal v l regulator. for buck converter operation, connect anode terminals of external bootstrap diodes to vdrv. for boost converter operation, connect vdrv to bst1/vdd1 and bst2/vdd2. bypass with a minimum 2.2? ceramic capacitor to pgnd_ (see the typical application circuit ). do not connect to an external supply . 28 cko clock output. cko is an output with twice the frequency of each converter (fsel_1 = v l ) and 90?out-of- phase with respect to converter 1. connect cko to the sync input of another MAX5098A for a four-phase converter. 29, 30 pgnd1, pgnd2 power ground. connect both pgnd1 and pgnd2 together and to the board power ground plane. 31 bst2/vdd2 converter 2 bootstrap flying-capacitor connection. for buck converter operation, connect bst2/vdd2 to a 0.1? ceramic capacitor and diode according to the typical application circuit . for boost converter operation, driver bypass capacitor connection. connect to vdrv and bypass with a 0.1? ceramic capacitor from bst2/vdd2 to pgnd_ (figure 6). ?p exposed pad. connect ep to sgnd. for enhanced thermal dissipation, connect ep to a copper area as large as possible. do not use ep as the sole ground connection.
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 13 functional diagram converter 1 comp1 pgood1 source1 drain1 v+ bypass fsel_1 en1 sync osc vdrv cko en2 drain2 pgood2 converter 2 vl cko2 ldo q s r 0.2v 0.74v 0.8v transconductance error amplifier f sw /4 frequency control pwm comparator cko1 maximum duty-cycle control fb1 v l vl bst1/vdd1 in_high on/off 0.9v pgnd_ current limit oscillator main oscillator gate overvoltage overvoltage startup circuit/ protection circuit/ charge pump 20v shunt regulator 1.8v sgnd q bst2/vdd2 source2 fb2 pgnd_ comp2 charge pump digital soft-start frequency divider MAX5098A
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 14 ______________________________________________________________________________________ detailed description pwm controller the MAX5098A dual dc-dc converter uses a pulse- width-modulation (pwm) voltage-mode control scheme. on each converter the device includes one integrated n-channel mosfet switch and requires an external low-forward-drop schottky diode for output rectifica- tion. the controller generates the clock signal by divid- ing down the internal oscillator (f cko ) or the sync input when driven by an external clock, therefore each controller? switching frequency equals half the oscilla- tor frequency (f sw = f cko /2) or half of the sync input frequency (f sw = f sync /2). an internal transconduc- tance error amplifier produces an integrated error volt- age at comp_, providing high dc accuracy. the voltage at comp_ sets the duty cycle using a pwm comparator and a ramp generator. at each rising edge of the clock, converter 1? mosfet switch turns on and remains on until either the appropriate or maximum duty cycle is reached, or the maximum current limit for the switch is reached. converter 2 operates 180 out- of-phase, so its mosfet switch turns on at each falling edge of the clock. in the case of buck operation (see the typical application circuit ), the internal mosfet is used in high-side configuration. during each mosfet? on- time, the associated inductor current ramps up. during the second half of the switching cycle, the high-side mosfet turns off and forward biases the schottky rec- tifier. during this time, the source_ voltage is clamped to a diode drop (v d ) below ground. a low for- ward voltage drop (0.4v) schottky diode must be used to ensure the source_ voltage does not go below -0.6v abs max. the inductor releases the stored energy as its current ramps down, and provides current to the output. the bootstrap capacitor is also recharged when the source_ voltage goes low during the high-side mosfet off-time. the maximum duty-cycle limit ensures proper bootstrap charging at startup or low input voltages. the circuit goes in discontinuous con- duction mode operation at light load, when the inductor current completely discharges before the next cycle commences. under overload conditions, when the inductor current exceeds the peak current limit of the respective switch, the high-side mosfet turns off quickly and waits until the next clock cycle. in the case of boost operation, the mosfet is a low- side switch (figure 6). during each on-time, the induc- tor current ramps up. during the second half of the switching cycle, the low-side switch turns off and for- ward biases the schottky diode. during this time, the drain_ voltage is clamped to a diode drop (v d ) above v out_ and the inductor provides energy to the output as well as replenishes the output capacitor charge. load-dump protection most automotive applications are powered by a multi- cell, 12v lead-acid battery with a voltage from 9v to 16v (depending on load current, charging status, tem- perature, battery age, etc.). the battery voltage is dis- tributed throughout the automobile and is locally regulated down to voltages required by the different system modules. load dump occurs when the alterna- tor is charging the battery and the battery becomes disconnected. power in the alternator inductance flows into the distributed power system and elevates the volt- age seen at each module. the voltage spikes have rise times typically greater than 5ms and decays within sev- eral hundred milliseconds but can extend out to 1s or more depending on the characteristics of the charging system. these transients are capable of destroying sensitive electronic equipment on the first fault event. during load dump, the MAX5098A provides the ability to clamp the input-voltage rail of the internal dc-dc converters to a safe level, while preventing power dis- continuity at the dc-dc converters?outputs. the load-dump protection circuit utilizes an internal charge pump to drive the gate of an external n-channel mosfet. this series protection mosfet absorbs the load-dump overvoltage transient and operates in satu- ration over the normal battery range to minimize power dissipation. during load dump, the gate voltage of the protection mosfet is regulated to prevent the source terminal from exceeding 19v. the dc-dc converters are powered from the source terminal of the load-dump protection mosfet, so that their input voltage is limited during load-dump and can operate normally. on/off the MAX5098A provides an input (on/off) to turn on and off the external load-dump protection mosfet. drive on/off high for normal operation. drive on/off low to turn off the external n-channel load-dump protec- tion mosfet and reduce the supply current to 7? (typ). when on/off is driven low, the converter also turns off, and the pgood_ outputs are driven low. v+ will be self discharged through the converters output currents and the ic supply current.
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 15 internal oscillator/out-of-phase operation the internal oscillator generates the 180 out-of-phase clock signal required by each regulator. the switching frequency of each converter (f sw ) is programmable from 200khz to 2.2mhz using a single 1% resistor at r osc . see the setting the switching frequency section. with dual synchronized out-of-phase operation, the MAX5098A? internal mosfets turn on 180 out-of- phase. the instantaneous input current peaks of both regulators do not overlap, resulting in reduced rms rip- ple current and input-voltage ripple. this reduces the required input capacitor ripple current rating, allows for fewer or less expensive capacitors, and reduces shielding requirements for emi. synchronization (sync)/ clock output (cko) the main oscillator can be synchronized to the system clock by applying an external clock (f sync ) at sync. the f sync frequency must be twice the required oper- ating frequency of an individual converter. use a ttl logic signal for the external clock with at least 100ns pulse width. r osc is still required when using external synchronization. program the internal oscillator fre- quency to have f sw = 1/2 f sync. the device is properly synchronized if the sync frequency, f sync , varies within ?0%. two MAX5098As can be connected in the master-slave configuration for four ripple-phase operation (figure 1). the MAX5098A provides a clock output (cko) that is 45 phase-shifted with respect to the internal switch turn-on edge. feed the cko of the master to the sync input of the slave. the effective input ripple switching frequency is four times the individual converter? switch- ing frequency. when driving the master converter using an external clock at sync, set the f sync clock duty cycle to 50% for effective 90 phase-shifted interleaved operation. when a sync is applied (and fsel_1 = 0), converter 1 duty cycle is limited to 75% (max). input voltage (v+)/ internal linear regulator (v l ) all internal control circuitry operates from an internally regulated nominal voltage of 5.2v (v l ). at higher input voltages (v+) of 5.2v to 19v, v l is regulated to 5.2v. at 5.2v or below, the internal linear regulator operates in dropout mode, where v l follows v+. depending on the load on v l , the dropout voltage can be high enough to reduce v l below the undervoltage lockout (uvlo) threshold. do not use v l to power external circuitry. for input voltages less than 5.5v, connect v+ and v l together. the load on v l is proportional to the switching frequency of converter 1 and converter 2. see the v l output voltage vs. converter switching frequency graph in the typical operating characteristics . for input voltage ranges higher than 5.5v, disconnect v l from v+. bypass v+ to sgnd with a 1? or greater ceramic capacitor placed close to the MAX5098A. bypass v l with a 4.7? ceramic capacitor to sgnd. undervoltage lockout/ soft-start/soft-stop the MAX5098A includes an undervoltage lockout with hysteresis and a power-on-reset circuit for converter turn-on and monotonic rise of the output voltage. the falling uvlo threshold is internally set to 4.1v (typ) with 180mv hysteresis. hysteresis at uvlo eliminates ?hat- tering?during startup. when v l drops below uvlo, the internal mosfet switches are turned off. the MAX5098A digital soft-start reduces input inrush currents and glitches at the input during turn-on. when uvlo is cleared and en_ is high, digital soft-start slow- ly ramps up the internal reference voltage in 64 steps. the total soft-start period is 4096 internal oscillator switching cycles. driving en_ low initiates digital soft-stop that slowly ramps down the internal reference voltage in 64 steps. the total soft-stop period is equal to the soft-start period. to calculate the soft-start/soft-stop period, use the fol- lowing equation: where f cko is the internal oscillator and f cko is twice each converters?switching frequency (fsel_1 = v l ) enable (en1, en2) the MAX5098A dual converter provides separate enable inputs, en1 and en2, to individually control or sequence the output voltages. these active-high enable inputs are ttl compatible. driving en_ high initiates soft-start of the converter, and pgood_ goes logic-high when the converter output voltage reaches the v tpgood_ threshold. driving en_ low initiates a soft- stop of the converter, and immediately forces pgood_ low. use en1, en2, and pgood1 for sequencing (see figure 2). connect pgood1 to en2 to make sure con- verter 1? output is within regulation before converter 2 starts. add an rc network from v l to en1 and en2 to delay the individual converter. sequencing reduces input inrush current and possible chattering. connect en_ to v l for always-on operation. tms f khz ss cko () () = 4096
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 16 ______________________________________________________________________________________ sync sync slave master v+ output4 output3 drain2 source2 drain1 source1 cko clkin v+ output2 output1 c in v in drain2 source2 drain1 source1 sync source1 (master) cko (master) source2 (master) source1 (slave) source2 (slave) cko (slave) c in (ripple) sync phase cko phase duty cycle = 50% figure 1. synchronized controllers
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 17 pgood_ converter 1 and converter 2 include a power-good flag, pgood1 and pgood2, respectively. since pgood_ is an open-drain output and can sink 3ma while provid- ing the ttl logic-low signal, pull pgood_ to a logic voltage to provide a logic-level output. pgood1 goes low when converter 1? feedback fb1 drops to 92.5% (v tpgood_ ) of its nominal set point. the same is true for converter 2. connect pgood_ to sgnd or leave unconnected if not used. current limit the internal mosfet switch current of each converter is monitored during its on-time. when the peak switch cur- rent crosses the current-limit threshold of 3.45a (typ) and 2.1a (typ) for converter 1 and converter 2, respectively, the on-cycle is terminated immediately and the inductor is allowed to discharge. the mosfet is turned on at the next clock pulse, initiating a new switching cycle. in deep overload or short-circuit conditions when the v fb_ voltage drops below 0.2v, the switching frequen- cy is reduced to 1/4 x f sw to provide sufficient time for the inductor to discharge. during overload conditions, if the voltage across the inductor is not high enough to allow for the inductor current to properly discharge, current runaway may occur. current runaway can destroy the device in spite of internal thermal-overload protection. reducing the switching frequency during overload conditions allows more time for inductor dis- charge and prevents current runaway. output overvoltage protection the MAX5098A outputs are protected from output volt- age overshoots due to input transients and shorting the output to a high voltage. when the output voltage rises above the overvoltage threshold, 110% (typ) nominal fb_, the overvoltage condition is triggered. when the overvoltage condition is triggered on either channel, both converters are immediately turned off, 20 pull- down switches from source_ to pgnd_ are turned on to help the output-voltage discharge, and the gate of the load-dump protection external mosfet is pulled low. the device restarts as soon as both converter out- puts discharge, bringing both fb_ input voltages below 12.5v of their nominal set points. thermal-overload protection during continuous short circuit or overload at the out- put, the power dissipation in the ic can exceed its limit. the MAX5098A provides thermal shutdown protection with temperature hysteresis. internal thermal shutdown is provided to avoid irreversible damage to the device. when the die temperature exceeds +165? (typ), an on-chip thermal sensor shuts down the device, forcing the internal switches to turn off, allowing the ic to cool. the thermal sensor turns the part on again with soft- start after the junction temperature cools by +20?. during thermal shutdown, both regulators shut down, pgood_ goes low, and soft-start resets. the internal 20v zener clamp from in_high to sgnd is not turned off during thermal shutdown because clamping action must be always active. fb1 fb2 en1 en2 v l r1 r2 c1 c2 v l v l v+ MAX5098A output2 output1 drain2 source2 drain1 source1 v in v l fb1 fb2 en1 en2 sequencing?utput 2 delayed with respect to output 1. r1/c1 and r2/c2 are sized for required sequencing. v l v l v l v+ MAX5098A output2 output1 drain2 source2 drain1 source1 pgood1 v in v l figure 2. power-supply sequencing configurations
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 18 ______________________________________________________________________________________ applications information setting the switching frequency the controller generates the clock signal by dividing down the internal oscillator f osc or the sync input sig- nal when driven by an external oscillator. the switching frequency equals half the internal oscillator frequency (f sw = f osc /2). the internal oscillator frequency is set by a resistor (r osc ) connected from osc to sgnd. to find r osc for each converter switching frequency f sw , use the formulas: a rising clock edge on sync is interpreted as a syn- chronization input. if the sync signal is lost, the inter- nal oscillator takes control of the switching rate, returning the switching frequency to that set by r osc . when an external synchronization signal is used, r osc must be selected such that f sw = 1/2 f sync . when f sync clock signal is applied, f cko equals f sync wave- form, phase shifted by 180? if the MAX5098A is run- ning without external synchronization, f cko equals the internal oscillator frequency f osc . buck converter effective input voltage range although the MAX5098A converter can operate from input supplies ranging from 5.2v to 19v, the input volt- age range can be effectively limited by the MAX5098A duty-cycle limitations for a given output voltage. the maximum input voltage is limited by the minimum on- time (t on(min) ): where t on(min) is 100ns. the minimum input voltage is limited by the maximum duty cycle (d max = 0.82): where v drop1 is the total parasitic voltage drops in the inductor discharge path, which includes the forward voltage drop (v d ) of the rectifier, the series resistance of the inductor, and the pcb resistance. v drop2 is the total resistance in the charging path that includes the on-resistance of the high-side switch, the series resis- tance of the inductor, and the pcb resistance. setting the output voltage for 0.8v or greater output voltages, connect a voltage- divider from out_ to fb_ to sgnd ( figure 3). select r b (fb_ to sgnd resistor) to between 1k and 20k . calculate r a (out_ to fb_ resistor) with the following equation: where v fb_ = 0.8v (see the electrical characteristics table) and v out_ can range from v fb_ to 28v (boost operation). for output voltages below 0.8v, set the MAX5098A out- put voltage by connecting a voltage-divider from out_ to fb_ to bypass ( figure 3). select r c (fb_ to bypass resistor) in the 50k range. calculate r a with the fol- lowing equation: where v fb_ = 0.8v, v bypass = 2v (see the electrical characteristics table), and v out_ can range from 0v to v fb_ . rr vv vv ac fb out bypass fb = ? ? ? ? ? ? ? ? ? ? __ _ rr v v ab out fb = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ _ 1 v vv d vv in min out drop max drop drop () = + ? ? ? ? ? ? + ? 1 21 v v tf in max out on min sw () () rk f mhz f mhz rk f mhz f mhz osc sw sw osc sw sw () = () () () = () < () 10 721 125 12 184 125 0 920 0 973 . . . . . . r a v out_ v out_ source_ fb_ v out_ 0.8v r b MAX5098A r c fb_ source_ bypass v out_ < 0.8v r a MAX5098A figure 3. adjustable output voltage
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 19 inductor selection three key inductor parameters must be specified for operation with the MAX5098A: inductance value (l), peak inductor current (i l ), and inductor saturation cur- rent (i sat ). the minimum required inductance is a func- tion of operating frequency, input-to-output voltage differential and the peak-to-peak inductor current ( i l ). a good compromise is to choose i l equal to 30% of the full load current. to calculate the inductance, use the following equation: where v in and v out are typical values (so that efficien- cy is optimum for typical conditions). the switching fre- quency is set by r osc (see the setting the switching frequency section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worse at the maximum input voltage. see the output capacitor section to verify that the worst-case output ripple is acceptable. the inductor saturation current is also important to avoid runaway current during output overload and continuous short circuit. select the i sat to be higher than the maximum peak current limits of 4.3a and 2.6a for converter 1 and converter 2. input capacitor the discontinuous input current waveform of the buck converter causes large ripple currents at the input. the switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple dictate the input capacitance requirement. note that the two converters of the MAX5098A run 180 out-of-phase, thereby effec- tively doubling the switching frequency at the input. the input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. the worst-case mismatch is when one converter is at full load while the other converter is at no load or in shutdown. the input ripple is comprised of v q (caused by the capacitor discharge) and v esr (caused by the esr of the capacitor). use ceramic capacitors with high ripple- current capability at the input, connected between drain_ and pgnd_. assume the contribution from the esr and capacitor discharge equal to 50%. calculate the input capacitance and esr required for a specified ripple using the following equations: where and where where i out is the maximum output current from either converter 1 or converter 2, and d is the duty cycle for that converter. the frequency of each individual con- verter is f sw . for example, at v in = 12v, v out = 3.3v at i out = 2a, and with l = 3.3?, the esr and input capacitance are calculated for a peak-to-peak input rip- ple of 100mv or less, yielding an esr and capacitance value of 20m and 6.8? for 1.25mhz frequency. at low input voltages, also add one electrolytic bulk capacitor of at least 100? on the converters?input voltage rail. this capacitor acts as an energy reservoir to avoid pos- sible undershoot below the undervoltage lockout thresh- old during power-on and transient loading. output capacitor the allowable output ripple voltage and the maximum deviation of the output voltage during step load cur- rents determines the output capacitance and its esr. the output ripple is comprised of v q (caused by the capacitor discharge) and v esr (caused by the esr of the capacitor). use low-esr ceramic or aluminum elec- trolytic capacitors at the output. for aluminum elec- trolytic capacitors, the entire output ripple is contributed by v esr . use the esr out equation to cal- culate the esr requirement and choose the capacitor accordingly. if using ceramic capacitors, assume the contribution to the output ripple voltage from the esr and the capacitor discharge are equal. calculate the output capacitance and esr required for a specified ripple using the following equations: esr v i c i vf out esr l out l qsw = = 8 d v v out in = c idd vf in out qsw = () ? 1 i vv v vf l l in out out in sw = () ? esr v i i in esr out l = + 2 l vvv vf i out in out in sw l = () ?
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 20 ______________________________________________________________________________________ where i l is the peak-to-peak inductor current as calculated above and f sw is the individual converter? switching frequency. the allowable deviation of the output voltage during fast transient loads also determines the output capaci- tance and its esr. the output capacitor supplies the step load current until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the convert- er. the high switching frequency of the MAX5098A allows for higher closed-loop bandwidth, reducing t response and the output capacitance requirement. the resistive drop across the output capacitor esr and the capacitor discharge causes a voltage droop during a step load. use a combination of low-esr tantalum or polymer and ceramic capacitors for better transient load and ripple/noise performance. keep the maximum output voltage deviation within the tolerable limits of the electronics being powered. when using a ceramic capacitor, assume 80% and 20% contribution from the output capacitance discharge and the esr drop, respectively. use the following equations to calculate the required esr and capacitance value: where i step is the load step and t response is the response time of the controller. controller response time depends on the control-loop bandwidth. boost converter the MAX5098A can be configured for step-up conver- sion since the internal mosfet can be used as a low- side switch. use the following equations to calculate the values for the inductor (l min ), input capacitor (c in ), and output capacitor (c out ) when using the converter in boost operation. inductor choose the minimum inductor value so the converter remains in continuous mode operation at minimum out- put current (i omin ). where the v d is the forward voltage drop of the external schottky diode, d is the duty cycle, and v ds is the volt- age drop across the internal mosfet switch. select the inductor with low dc resistance and with a satura- tion current (i sat ) rating higher than the peak switch current limit of 4.3a (i cl1 ) and 2.6a (i cl2 ) of converter 1 and converter 2, respectively. input capacitor the input current for the boost converter is continuous and the rms ripple current at the input is low. calculate the capacitor value and esr of the input capacitor using the following equations. where where v ds is the voltage drop across the internal mosfet switch. i l is the peak-to-peak inductor ripple current as calculated above. v q is the portion of input ripple due to the capacitor discharge and v esr is the contribution due to esr of the capacitor. output capacitor for the boost converter, the output capacitor supplies the load current when the main switch is on. the required output capacitance is high, especially at high- er duty cycles. also, the output capacitor esr needs to be low enough to minimize the voltage drop due to the esr while supporting the load current. use the follow- ing equation to calculate the output capacitor for a specified output ripple tolerance. where i pk is the peak inductor current as defined in the power dissipation section for the boost converter, i o is the load current, v q is the portion of the ripple due to esr v i c id vf esr pk out o max qsw = = i vv d lf l in ds sw = () ? c i fv esr v i in l sw q esr l = = 8 d vvv vvv od in odds = + + ? ? l vd fvi min in sw o omin = 2 2 esr v i c it v out esr step out step response q = = ?? vvv o ripple esr q _ ?+
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 21 the capacitor discharge, and v esr is the contribution due to the esr of the capacitor. d max is the maximum duty cycle at minimum input voltage. power dissipation the MAX5098A includes two internal power mosfet switches. the dc loss is a function of the rms current in the switch while the switching loss is a function of switch- ing frequency and instantaneous switch voltage and cur- rent. use the following equations to calculate the rms current, dc loss, and switching loss of each converter. the MAX5098A is available in a thermally enhanced package and can dissipate up to 2.7w at +70? ambient temperature. the total power dissipation in the package must be limited so that the operating junction tempera- ture does not exceed its absolute maximum rating of +150? at maximum ambient temperature. for the buck converter: where see the electrical characteristics table for the r on(max) maximum value. for the boost converter: where v ds is the drop across the internal mosfet and is the efficiency. see the electrical characteristics table for the r on(max) value. where t r and t f are rise and fall times of the internal mosfet. t f can be measured in the actual application. the supply current in the MAX5098A is dependent on the switching frequency. see the typical operating characteristics to find the supply current of the MAX5098A at a given operating frequency. the power dissipation (p s ) in the device due to supply current (i supply ) is calculated using following equation. p s = v inmax x i supply the total power dissipation p t in the device is: p t = p dc1 + p dc2 + p sw1 + p sw2 + p s where p dc1 and p dc2 are dc losses in converter 1 and converter 2, respectively. p sw1 and p sw2 are switching losses in converter 1 and converter 2, respectively. calculate the temperature rise of the die using the fol- lowing equation: t j = t c x (p t x jc ) where jc is the junction-to-case thermal impedance of the package equal to +1.7?/w. solder the exposed pad of the package to a large copper area to minimize the case-to-ambient thermal impedance. measure the temperature of the copper area near the device at a worst-case condition of power dissipation and use +1.7?/w as jc thermal impedance. compensation the MAX5098A provides an internal transconductance amplifier with its inverting input and its output available for external frequency compensation. the flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. for cost-sensitive applications, use aluminum electrolytic capacitors; for component size- sensitive applications, use low-esr tantalum, polymer, or ceramic capacitors at the output. the high switching frequency of MAX5098A allows use of ceramic capaci- tors at the output. choose all the passive power components that meet the output ripple, component size, and component cost requirements. choose the small-signal components for the error amplifier to achieve the desired closed-loop p vi tt f sw oin r f sw = + () 4 iiiii d i vi v i vv d lf ii i ii i pi r rms dc pk dc pk max in oo in l in ds sw dc in l pk in l dc rms ds on max =++ () () = = () = =+ = ? ? 22 2 3 2 2 ()( ) ii i ii i p vi tt f dc o l pk o l sw in o r f sw = =+ = + () ? 2 2 4 iiiii d pi r rms dc pk dc pk max dc rms ds on max =++ () ? ? ? ? = 22 2 3 ()
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 22 ______________________________________________________________________________________ bandwidth and phase margin. use a simple pole-zero pair (type ii) compensation if the output capacitor esr zero frequency is below the unity-gain crossover fre- quency (f c ). type iii compensation is necessary when the esr zero frequency is higher than f c or when com- pensating for a continuous mode boost converter that has a right-half-plane zero. use procedure 1 to calculate the compensation net- work components when f zero,esr < f c . buck converter compensation procedure 1 (see figure 4) 1) calculate the f zero,esr and lc double-pole fre- quencies: 2) select the unity-gain crossover frequency: if the f zero,esr is lower than f c and close to f lc , use a type ii compensation network where r f c f provides a midband zero f mid,zero , and r f c cf provides a high- frequency pole. 3) calculate modulator gain g m at the crossover fre- quency. where v osc is a peak-to-peak ramp amplitude equal to 1v. the transconductance error amplifier gain is: g e/a = g m x r f the total loop gain at f c should be equal to 1: g m x g e/a = 1 or 4) place a zero at or below the lc double pole: 5) place a high-frequency pole at f p = 0.5 x f sw . procedure 2 (see figure 5) if the output capacitor used is a low-esr ceramic type, the esr frequency is usually far away from the targeted unity crossover frequency (f c ). in this case, type iii compensation is recommended. type iii compensation provides two-pole zero pairs. the locations of the zero and poles should be such that the phase margin peaks around f c . it is also important to place the two zeros at or below the double pole to avoid the conditional stabil- ity issue. 1) select a crossover frequency: 2) calculate the lc double-pole frequency, f lc : f lc lc out out = 1 2 f f c sw 20 c c frc cf f sw f f = () ? 205 1 . c rf f flc = 1 2 r v esr f l v v g esr f osc c out out in m = + () 2 08 . g v v esr esr f l v m in osc c out out = + () 2 08 . f f c sw 20 f esr c f lc zero esr out lc out out , = = 1 2 1 2 r 1 fb_ r f comp_ v out v ref c cf c f r 2 - + g m figure 4. type ii compensation network
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 23 3) place a zero where and r f 10k . 4) calculate c i for a target unity crossover frequency, f c . 5) place a pole or 5 x f c , whichever is lower, 6) place a second zero, f z2 , at 0.2 x f c or at f lc , whichever is lower. 7) place a second pole at 1/2 the switching frequency. boost converter compensation the boost converter compensation gets complicated due to the presence of a right-half-plane zero f zero,rhp . the right-half-plane zero causes a drop in phase while adding positive (+1) slope to the gain curve. it is important to drop the gain significantly below unity before the rhp frequency. use the following pro- cedure to calculate the compensation components: 1) calculate the lc double-pole frequency, f lc , and the right-half-plane-zero frequency. where d v v r v i in out min out out max = = ? () 1 () f dr l zero rhp min out , = () ? () 1 2 2 f d lc lc out out = ? 1 2 c c frc cf f sw f f = () ? 205 1 . r fc r zi i 1 1 2 2 = ? r fc i pi = 1 2 1 c fl c v vr i c out out osc in f = 2 c fr f lc f = 1 2075 . f rc at f z ff lc 1 1 2 075 = .. r1 r f comp_ v out v ref r2 r i c i c f c cf - + g m fb_ figure 5. type iii compensation network pgnd_ drain_ MAX5098A v l vdrv v+ v out_ bst_/vdd_ c out sgnd pgnd_ drain_ source_ source_ fb_ figure 6. boost application f rc at f p ii zero esr 1 1 2 = ,
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 24 ______________________________________________________________________________________ target the unity-gain crossover frequency for: 2) place a zero where r f 10k . 3) calculate c i for a target crossover frequency, f c : where c = 2 x f c : 4) place a pole 5) place the second zero where 6) place the second pole the switching frequency. load-dump protection mosfet select the external mosfet with an adequate voltage rating, v dss , to withstand the maximum expected load- dump input voltage. the on-resistance of the mosfet, r ds(on) , should be low enough to maintain a minimal voltage drop at full load, limiting the power dissipation of the mosfet. during regular operation, the power dissipated by the mosfet is: p normal = i load 2 x r ds(on) where i load is equal to the sum of both converters input currents. the mosfet operates in a saturation region during load dump, with both high voltage and current applied. choose a suitable power mosfet that can safely oper- ate in the saturation region. verify its capability to sup- port the downstream dc-dc converters input current during the load-dump event by checking its safe oper- ating area (soa) characteristics. since the transient peak power dissipation on the mosfet can be very high during the load-dump event, also refer to the ther- mal impedance graph given in the data sheet of the power mosfet to make sure its transient power dissi- pation is kept within the recommended limits. improving noise immunity in applications where the MAX5098A is subject to noisy environments, adjust the controller? compensation to improve the system? noise immunity. in particular, high- frequency noise coupled into the feedback loop causes jittery duty cycles. one solution is to lower the crossover frequency (see the compensation section). c c frc cf f sw f f = () ? 205 1 . f rc at p fcf 2 1 2 12 = / r fc r lc i i 1 1 2 = ? f rc at f z i lc 2 1 21 = . r fc i zero rhp i = 1 2 , f rc at f p ii zero rhp 1 1 2 = . , c vdlc rv i osc c out out cfin = () + ? ? ? ? ? ? ? 1 2 2 c fr f lc f = 1 2075 . f rc at f z ff lc 1 1 2 075 = . . f f c zero rhp , 5
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 25 pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. this is especially true for dual converters where one channel can affect the other. refer to the max5099 evaluation kit data sheet for a specific layout example. use a multilayer board whenever possible for better noise immunity. follow these guidelines for good pcb layout: 1) for sgnd, use a large copper plane under the ic and solder it to the exposed paddle. to effectively use this copper area as a heat exchanger between the pcb and ambient, expose this copper area on the top and bottom side of the pcb. do not make a direct connection from the exposed pad copper plane to sgnd underneath the ic. 2) isolate the power components and high-current path from the sensitive analog circuitry. 3) keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. 4) connect sgnd and pgnd_ together at a single point. do not connect them together anywhere else (refer to the max5099 evaluation kit data sheet for more information). 5) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs (2oz vs. 1oz) to enhance full- load efficiency. 6) ensure that the feedback connection to c out is short and direct. 7) route high-speed switching nodes (bst_/vdd_, source_) away from the sensitive analog areas (bypass, comp_, and fb_). use the internal pcb layer for sgnd as an emi shield to keep radiated noise away from the ic, feedback dividers, and analog bypass capacitors. layout procedure 1) place the power components first, with ground ter- minals adjacent (inductor, c in_ , and c out_ ). make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) group the gate-drive components (bootstrap diodes and capacitors, and v l bypass capacitor) together near the controller ic. 3) make the dc-dc controller ground connections as follows: a) create a small, signal ground plane underneath the ic. b) connect this plane to sgnd and use this plane for the ground connection for the reference (bypass), enable, compensation components, feedback dividers, and osc resistor. c) connect sgnd and pgnd_ together (this is the only connection between sgnd and pgnd_). refer to the max5099 evaluation kit data sheet for more information.
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection 26 ______________________________________________________________________________________ bst2/vdd2 source2 source2 pgnd1 fb2 comp2 pgood2 en2 sync 31 1 32 29 6 7 4 5 9 c6 d1 26 25 24 28 d2 c7 l1 c20 c9 r9 c8 r6 r22 r7 r8 r12 c11 c12 c13 19 18 21 vout1 pgnd sgnd 20 17 clock out v l v in vdrv bst1/vdd1 source1 source1 cko fb1 comp1 pgood1 en1 fsel_1 in_high on/off gate v+ drain1 drain1 drain2 drain2 osc bypass sgnd vdrv v l 12 22 23 2 3 11 10 13 c1 c19 c4 c15 8 16 15 14 27 pgnd2 30 v in = 4.5v to 5.5v MAX5098A vin pgnd c14 d4 d5 c5 l2 c21 c17 r18 c16 r15 r23 r16 r17 vout2 pgnd sgnd vdrv figure 7. 4.5v to 5.5v operation
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection ______________________________________________________________________________________ 27 bst2/vdd2 source2 source2 pgnd1 fb2 comp2 pgood2 en2 sync 31 1 32 29 6 7 4 5 9 c6 0.1 f d1 26 25 24 28 d2 c7 22 f c2 4.7 f 35v l1 4.7 h c20 33pf c9 2700pf r9 12.7 c8 270pf r6 52.3k 1% r22 10k 1% r7 10k 1% r8 976 1% r12 6.49 c11 0.22 f c12 2.2 f c13 4.7 f 19 18 21 vout1 pgnd sgnd 20 17 clock out v l vdrv bst1/vdd1 source1 source1 cko fb1 comp1 pgood1 en1 fsel_1 in_high on/off gate v+ drain1 drain1 drain2 drain2 osc bypass sgnd vdrv v l n1 r1 3.9k 12 22 23 2 3 11 10 13 c1 22 f 100v c3 150 f 25v c19 1 f 25v c4 10 f 25v c15 10 f 25v 8 16 vdrv 15 14 27 pgnd2 30 v in = 5.2v to 19v vout1 = 5v at 2a r21 1 MAX5098A vin pgnd c14 0.1 f d4 d5 c5 22 f l2 4.7 h c21 56pf c17 2700pf r18 7.15 c16 270pf r15 37.4k 1% r23 10k 1% r16 12.1k 1% r17 976 1% vout2 pgnd sgnd vdrv vout2 = 3.3v at 1a typical application circuit
MAX5098A dual, 2.2mhz, automotive buck or boost converter with 80v load-dump protection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. MAX5098A tqfn (5mm x 5mm) top view 29 30 + 28 27 *ep *ep = exposed pad. 12 11 13 drain2 pgood2 en2 fb2 comp2 14 source2 drain1 pgood1 en1 source1 fb1 comp1 12 cko 4567 23 24 22 20 19 18 pgnd1 pgnd2 v l v+ in_high on/off drain2 drain1 3 21 31 10 bst2/vdd2 gate 32 9 source2 sync vdrv 26 15 sgnd bst1/vdd1 25 16 bypass osc fsel_1 8 17 source1 pin configuration chip information process: bicmos package information for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 32 tqfn t3255+4 21-0140

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